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page 1 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 description the raa23022x and raa23023x are dual step-down dc/dc converter, 4.5v to 16v input voltage rage and 3a output current. auto pfm mode makes devices low power operation at light load, so it makes a system lower power. the raa23022x is suitable for battery backup system using lithium primary cell with built-in battery backup circuit. features z dc/dc input voltage range 4.5v to 16v shutdown current 1ua (typ.) auto pfm mode maximum output current 3a synchronous rectification type step-down dc/dc integrated power mosfets switching frequency 1.1mhz (fixed) output voltage range 0.8v to 6v internal phase compensator soft start 2ms (fixed) discharge circuit power good battery backup circuit (raa23022x) z protection circuit short circuit protection (latch type) thermal shutdown circuit 165 c (typ.) under voltage lockout circuit (recovery type) z package 20-pin htssop application communication (router, home gate way, radio, etc.) industrial (surveillance camera, various controller, etc.) building (security device, emergency device, various controller, etc.) oa (printer, plane paper copier, etc.) smart meter smart home appliances and, usable various application note: the information contained in this document is being i ssued in advance of the production cycle for the product. the parameters for the product may cha nge before final production, or renesa s electronics corporation, at its own discretion, may withdraw the product prior to its production. a quality grade of these ics is ?standard?. recommended applications are indicated below. computers, office equipment, communica tions equipment, test and measurement equipment, audio and visual equipment, home electronic appl iances, machine tools, personal electronic equipment, and industrial robots, etc. raa23022x raa23023x [under development] 16v input, 3a, dual step-down dc/dc converter + batter y backu p r18ds0017ej0000 rev.0.00 a u g .19.2014 preliminary datasheet
page 2 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 product lineup table part number output type vin range vout iout (max.) switching frequency raa230221 2 step-down + bb 4.5 to 16v ch1 3.3v (fixed) ch2 0.8v to 6.0v* 1 3a 1.1mhz raa230222 2 step-down + bb 4.5 to 16v ch1 3.3v (fixed) ch2 5.0v (fixed) 3a 1.1mhz RAA230223 2 step-down + bb 4.5 to 16v ch1 and ch2 0.8v to 6.0v* 1 3a 1.1mhz raa230231 2 step-down 4.5 to 16v ch1 3.3v (fixed) ch2 0.8v to 6.0v* 1 3a 1.1mhz raa230232 2 step-down 4.5 to 16v ch1 3.3v (fixed) ch2 5.0v (fixed) 3a 1.1mhz raa230233 2 step-down 4.5 to 16v ch1 and ch2 0.8v to 6.0v* 1 3a 1.1mhz note bb : battery backup *1 set by exte rnal resistors
page 3 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 circuit example raa23022x (2ch dcdc + battery backup, vout set by external resistors) raa23023x (2ch dcdc, vout set by external resistors)
page 4 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 block diagram raa23022x (2ch dcdc + battery backup, vout set by external resistors)
page 5 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 raa23023x (2ch dcdc, vout set by external resistors)
page 6 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 pin function raa23022x (2ch dcdc + battery backup) pin no. symbol i/o function 1 pgnd1 i/o ch1 power ground 2 lx1 o ch1 inductor connection 3 boost1 i ch1 boot strap input (connect 0.1uf capacitor between lx1 and boost1) 4 vin1 i ch1 power supply 5 vout1 i ch1 vout feedback 6 fb1 i ch1 feedback resistor connection 7 gnd i/o analog ground 8 vreg o internal power supply output (connect 1uf capacitor between vreg and agnd) 9 pgood o power good output (open drain) ch1 and ch2 stop :l ch1 or ch2 operation : hiz 10 x_autopfm i auto pfm mode on/off x_autopfm=?l? : auto pfm mode (change automatically) pfm mode at light load pwm mode at heavy load x_autopfm=?h? : pwm mode (fixed) 11 vbb_in i battery connection 12 vbb_out o backup voltage output 13 en1 i ch1 enable en1=?l? or open : ch1 stop en1=?h? : ch1 operation 14 en2 i ch2 enable en2=?l? or open : ch2 stop en2=?h? : ch2 operation 15 fb2 i ch2 feedback resistor connection 16 vout2 i ch2 vout feedback 17 vin2 i ch2 power supply 18 boost2 i ch2 boot strap input (connect 0.1uf capacitor between lx2 and boost2) 19 lx2 o ch2 inductor connection 20 pgnd2 i/o ch2 power ground
page 7 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 raa23023x (2ch dcdc) pin no. symbol i/o function 1 pgnd1 i/o ch1 power ground 2 lx1 o ch1 inductor connection 3 boost1 i ch1 boot strap input (connect 0.1uf capacitor between lx1 and boost1) 4 vin1 i ch1 power supply 5 vout1 i ch1 vout feedback 6 fb1 i ch1 feedback resistor connection 7 gnd i/o analog ground 8 vreg o internal power supply output (connect 1uf capacitor between vreg and agnd) 9 pgood o power good output (open drain) ch1 and ch2 stop :l ch1 or ch2 operation : hiz 10 x_autopfm i auto pfm mode on/off x_autopfm=?l? : auto pfm mode (change automatically) pfm mode at light load pwm mode at heavy load x_autopfm=?h? : pwm mode (fixed) 11 gnd i/o analog ground 12 gnd i/o analog ground 13 en1 i ch1 enable en1=?l? or open : ch1 stop en1=?h? : ch1 operation 14 en2 i ch2 enable en2=?l? or open : ch2 stop en2=?h? : ch2 operation 15 fb2 i ch2 feedback resistor connection 16 vout2 i ch2 vout feedback 17 vin2 i ch2 power supply 18 boost2 i ch2 boot strap input (connect 0.1uf capacitor between lx2 and boost2) 19 lx2 o ch2 inductor connection 20 pgnd2 i/o ch2 power ground
page 8 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 absolute maximum ratings (unless otherwise specified, ta = 25c,) parameter symbol ratings unit condition vin applied voltage vin -0.3 to +17.6 v vin1, vin2 en applied voltage en -0.3 to +17.6 v en1, en2 x_autopfm applied voltage x_autopfm -0.3 to +17.6 v x_autopfm pgood voltage pgood t.b.d. v pgood fb applied voltage fb -0.3 to +6.5 v fb1, fb2 vout applied voltage vout -0.3 to +6.5 v vout1, vout2 vbb_in applied voltage (raa23022x) vbb_in -0.3 to +6.5 v vbb_in vin input current(peak) ivin (peak)- 4.2 a vin1, vin2 lx output current(peak) ilx(peak)+ 4.2 a lx1, lx2 vout sink current (dc) ivout(dc)- (100) ma vout1, vout2 when discharge circuit operation gnd voltage gnd -0.3 to +0.3 v pgnd1, pgnd2, gnd total power dissipation pt t.b.d. *1 mw ta Q 25 operating ambient temperatur e ta -40 to (+85) c operation junction temperature tj -40 to (+125) c storage temperature tstg -55 to +150 c note: t.b.d. :to be determined. *1 this is the value at t a < +25c. at t a > +25c, the total power dissipation decrease with -t.b.d. mw/c. caution: product quality may suffer if the absolute maximum rating is exceed ed even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditio ns that ensure that the absolute maximum ratings are not exceeded.
page 9 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 recommended operating condition (unless otherwise specified, ta = 25c) parameter symbol min. typ. max. unit condition vin applied voltage vin 4.5 16.0 v vin1, vin2 en applied voltage en 0 16.0 v en1, en2 x_autopfm applied voltage x_autopfm 0 16.0 v x_autopfm pgood voltage pgood 0 t. b. d . v pgood fb applied voltage fb 0 6.0 v fb1, fb2 vout setting range vdcdc_ext see diagram below 6.0 v at external resistor setting note: t.b.d. :to be determined. minimum value of vout setting range (t.b.d.) 9v (t.b.d.) can be set
page 10 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 electrical characteristics (unless otherwise specified, ta = 25c, vin1 = vin2 = 12v) parameter symbol min. typ. max. unit condition to ta l shutdown current idd(shdn) 1 10 ua en1 = en2 = gnd under voltage lock out circuit (uvlo) operating start voltage vdet(vin) 3.5 3.8 4.1 v vin1 and vin2 rising are detected vin hysteresis vhys(vin) 0.24 0.30 0.36 v vin1 and vin2 falling are detected internal power supply (vreg) internal power supply voltage vreg 4.7 5.0 5.3 v ireg = 0ma, vin1 = 6v to 16v output (pwm mode) e/a feedback voltage vref07 (0.693) 0.700 (0.707) v include input offset at external resistor setting output voltage accuracy vacc (-2.5) (+2.5) % fixed vout products high side fet on-resistance ronh 100 m vin1, vin2 = 6v to 16v low side fet on-resistance ronl 70 m vin1, vin2 = 6v to 16v discharge circuit on-resistance rondc (100) (200) ch1, ch2 soft start soft start time tss 2 ms thermal shutdown circuit detect temperature *1 165 c hysteresis temperature *1 20 c logic input high level threshold voltage vih 1.3 vin+0.3 v en1, en2, x_autopfm low level threshold voltage vil -0.3 0.4 v en1, en2, x_autopfm input current ien 1 ua en1 = 3.3v, en2 = 3.3v x_autopfm = 3.3v battery backup (raa23022x) vbb_in input voltage range vbb 2.7 3.0 3.7 v on-resistance between vbb_in and vbb_out ron_vbat 400 vbb_out = vbb_in on-resistance between vout1 and vbb_out ron_vout1 (90) vbb_out = vout1 (vbb leak current ) il_bb t. b . d . ua vbb_out = vbb_in = 3.0v note: t.b.d. :to be determined. *1 not production tested.
page 11 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 typical performance characteristics (unless otherwise specified, t a = 25c) efficiency vs. output current vin=12 v vout=5.0v vout=3.3v vout=1.2v
page 12 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 detailed description control block en1, en2 : on/off setting en1 en2 state vreg l l shutdown (ch1 and ch2 stop) 0v h l ch1 operation ch2 stop 5.0v h h ch1 and ch2 operation 5.0v l h ch1 stop ch2 operation 5.0v note: l: low level, h: high level x_autopfm : autopfm mode/ pwm mode setting x_autopfm operation l auto pfm mode (change automatically) pfm mode at light load pwm mode at heavy load h pwm mode (fixed) note: l: low level, h: high level pgood : power good output state pgood ch1 and ch2 stop l ch1 or ch2 operation hiz note: l: low level, h: high level when vreg voltage falls und er t.b.d. v, pgood pin becomes hi gh impedance thou gh ch1 and ch2 are low. when using this function, connect pgood pin to vreg, vout1, vout2, etc.
page 13 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 auto pfm mode raa23022x and raa23023x have auto pfm mode to achieve high efficiency over a wide load current range. the devices operate with pfm (pulse frequency modulation) mode at light load current, and pwm (pulse width modulation) mode at heavy load current. an operation mode is automatically switched de pending on load current. when a bottom of inductor ripple current is under 0a, reverse current flow at low-side n-channel mosfet of output block. the devices operate with pfm mode during detecting this current. a current of switching pfm / pwm mode (i change ) is calculated by an equation below. l : inductance, f sw : 1.1mhz raa23022x and raa23023x have x_autopfm pin. wh en low level, the devices operate auto pfm mode (pfm mode / pwm mode changed automatica lly). when high level, the devices operate pwm mode, then not change into auto pfm mode. raa23022x raa23023x reverse current detect switching voltage inductor current reverse current reverse current flow when a bottom of inductor ripple current is under 0a.
page 14 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 soft start to limit the startup inrush current and output voltage overshoot, a soft start circuit is used to ramp up the reference voltage from 0 v to its final value linearly. when en pin is set from low level to high level, the device starts operation an d output voltage rises with soft start. both ch1 and ch2 soft start time are fixed at 2ms(typ.) an d no additional components are needed. soft start feature gradually increases the error amplif ier (e/a) input threshold voltage by using the voltage that is generated by the digital soft start (dss) circuit. v out fb1, fb2 e/a1, e/a2 - + dss circuit 0.7v en1 vout1 vreg dss 0.7v lx1 2ms note1 : this figure is the case of RAA230223 or raa230233. note2 : this chart shows ch1 starting. note3 : dss waveform cannot be observed from ic outside.
page 15 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 discharge circuit the device has discharge circuit in both ch1 and ch2. this enables a rapid discharge without an external mosfet. when an en pin is changed from high level to low, each discharge switch in vout pin is turned on and all capacitors which are connected to each output are rapidly discharged through vout pin. when vin pin voltage becomes low level, discharge switches become off because there are no voltage to keep them on. the control voltage of discharge switches is vreg, and the discharge time of vreg capacitor is over 100ms when vin volt age falls down, so even if en pin is connected to vin pin, an output voltage can be discharged because vreg voltage level can keep the discharge switches on. when vreg voltage falls, vout pin becomes high impedance. discharge time can be calculated by an equation below. v dc is a voltage after t dc (s). c all is sum of all capacitance which are connected to ch1 or ch2 output (output capacitor, bypass capacitor around mcu, etc.). r ondc is on resistance of discharge circuit. pgnd1 lx1 vin1 ch1 output control vin device b device a device c vreg discharge control vout1 pgnd2 lx2 vin2 ch2 output control device e device d device f vout2 discharge control note : these dashed arrows are discharge line.
page 16 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 power good power good is an open-drain output that requires a pull ? up resistor (recommended value = 100k ? ). pgood pin becomes high impedance (hiz) wh en either ch1 or ch2 fb pin voltage and thus its output voltage rises above t.b.d.% of nomi nal regulation point. if it is pulled-up, pgood output high level. pgood pin goes low when both ch1 or ch2 output voltage falls below t.b.d.% of the regulation point. when both en1 and en2 pin goes low level, pgood pin becomes hiz because vreg is used for power good control and it fall down at this time. so, if pgood pin is connected to vin, its status becomes high level even if ch1 and ch2 stop. pgood pin must be pulled up to ch1 output, ch2 output or vreg when using this function. ch1 and ch2 can be started in order by connecting pgood pin to en1 or en2. this function can be also used for sequence signal for other devices. ch1 en1 en1 vout1 vreg 2ms ch2 en2 100k ? pgood vreg 1uf power good control vreg pgood en2 2ms vout2 (1ms) circuit example when ch2 is started after ch1
page 17 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 battery backup (raa23022x) raa23022x has a battery backup circuit which is used to operate some devices at system power-off. the circuit can be easily designed by raa23022x without two diodes. when ch1 operates, vbb_out = vout1. when ch1 stops and vout1 pin voltage is higher than vbb_in pin, vbb_out = vout1 pin. when ch1 stops and vout1 pin voltage is lower than vbb_in pin, vbb_out = vbb_in pin. vbb_out voltage value is dependent on on-resistance between vbb_in and vbb_out, on-resistance between vout1 and vbb_out and vbb_out output current. vbb_out can be calculated by equations below. 1. normal operation mode (vbb_out = vout1) 2. battery backup mode (vbb_out = vbb_in) v bb_out : vbb_out voltage (v) v out1 : vout1 voltage = ch1 output voltage (v) v bb_in : vbb_in voltage = battery voltage (v) i bb_out : vbb_out output current (a) r on_vout1 : on resistance between vout1 and vbb_out 90 ? (typ.) r on_vbat : on resistance between vbb_in and vbb_out 400 ? (typ.) note : t.b.d. (1.8v) v bb_out 3.7v connect t.b.d. nf capacitor to vbb_out pin. note : pok1 is an ic internal signal which identifies ch1 operating status. it cannot be seen from ic outside. after ch1 has started up, there is about 1ms delay time till pok1 becomes high level. vbb_out pin output status ch1 vout1, vbb_in vbb_out operation (pok1 = h) vout1 vbb_in or vout1 < vbb_in vout1 stop (pok1 = l) vout1 vbb_in vout1 vout1 < vbb_in vbb_in note : l: low level, h: high level
page 18 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 timing chart of battery backup 1. with 3.0v battery 2. with 3.6v battery
page 19 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 protection circuit view protection circuit function operation status reset common circuit (vreg, etc.) ch1, ch2 output short circuit protection (scp) detect output voltage dropping because of short circuit, etc. (latch type) operation latched to off turn en1 and en2 pin from high level to low level or drop vin1 and vin2 pin voltage under operation stop voltage of uvlo thermal shutdown circuit (tsd) detect rise up of ic internal temperature (over 165 ? c) (auto recovery type) operation stop the temperature falls under voltage lockout circuit (uvlo) detect dropping of vin (auto recovery type) operation stop up vin1 and vin2 over operating start voltage (3.8v) note scp : short circuit protection tsd : thermal shutdown circuit uvlo : under voltage lockout circuit short circuit protection (latch type) when ch1 or ch2 output voltage drops, each fb pi n input voltage also drops. if this voltage falls below the input detection voltage of the short circuit protection, the outputs both ch1 and ch2 are stopped (latched to off). at this time, common circuits (such as vreg, etc.) continue operating. when the protection is operating, to reset the latch, either turn the en1 pin and en2 pin from high to low or drop the vin1 pin and vin2 voltage under operation stop voltage of uvlo.
page 20 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 thermal shutdown circuit (auto recovery type) when overheating has been detected (d etect temperature: 165c ), the outputs both ch1 and ch2 is stopped. then, power mosfet of output both high side and low side are turned off. common circuits (such as vreg, etc.) continue operating. if the device temperature falls and becomes under detect temperature, the protection is canceled and output automatically resumes. under voltage lockout circuit (auto recovery type) (1) under voltage lockout operation when the power supply voltage (vin1 and vin2) falls to the operation stop voltage (t.b.d.), output from all channels stops. common circuits (such as vreg, etc.) continue operating. (2) restoring output once vin1 and vin2 is restored to the operating start voltage (3.8v), the under voltage lockout operation is canceled and output automatically re sumes. the output voltage cannot be restored while the under voltage lockout circuit is operating, not even by manipulating the en pin. current limiting if an overcurrent occurs, an output current is limited on a pulse-by-pulse basis. if th e current sensor detects an overcurrent, the current is limited and the switching operation of the power mosfet in the output stage stops until the next cycle. when an output current is limited, the output voltage drops. if a fb pin voltage falls below the input detection voltage, the short-circuit protection circuit starts operating.
page 21 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 guide for circuit design setting output voltage (when the output voltage is set by external resistor) the output voltage can be calcu lated by an equation below. vout = 0.7 x (1 + r1 / r2) examples of r1 and r2 selection vout 0.9v 1.0v 1.05v 1.1v 1.18v 1.2v 1.5v 1. 8v 2.5v 3.3v 5.0v r1 180k 220k 180k 270k 270k 130k 150k 470k 620k 820k 680k r2 620k 510k 360k 470k 390k 180k 130k 300k 240k 220k 110k output voltage accuracy (when the output voltage is set by external resistor) output voltage accuracy can be calculated by an equation below. v outacc is the output voltage accuracy (%). v ithacc is the e/a input threshold voltage accuracy (%). v out is the output voltage (v). r acc is the external resistor accuracy (%). so, an output voltage accuracy of the device is below. note : these equation don?t include vout fluctuation by load step transient. - + 0.7v vout r1 r2
page 22 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 inductor selection an inductor target is that ripple current ( ? il) of inductor becomes 10 to 40 % of iout(max). when ? il increases, inductor current peak raises, so ripple of vout gets larger and power loss increases. but, large size inductor is required to lower ? il. ? il can be calculated by an equation below. fsw is 1.1mhz. peak current of inductor (ilpeak) can be calculated by an equation below. choose a inductor which saturation current is higher than ilpeak . inductor example note i temp : rated current by temperature rising i sat : rated current by inductance loss these inductors are examples. about in ductor detail, contact each manufacturer inductance (uh) inductor manufacturer i temp (a) i sat (a) size (lxwxt, mm) 2.2 nrs5024t2r2nmgj taiyo yuden 3.1 4.1 4.9x4.9x2.4 2.2 744778002 wurth 4.0 4.8 7.3x7.3x3.2 3.3 nrs5030t3r3mmgj taiyo yuden 3.0 3.6 4.9x4.9x3.1 3.3 7447789003 wurth 3.4 4.2 7.3x7.3x3.2 4.7 nrs5040t4r7nmgk taiyo yuden 3.1 3.3 4.9x4.9x4.1 4.7 744777004 wurth 4.0 4.0 7.3x7.3x4.3
page 23 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 output capacitor selection raa23022x and raa23023x have a phase compensation ci rcuit which is optimized to dc/dc operation. in order to operate stably with the phase compensation, connect the output capacitor which is over 22 uf. ceramic capacitor can be used for output capacitor. it has low esr, so vout ripple is decreased. vout ripple ( ? vrpl) can be calculated by an equation below. esr : equivalent series resistance input capacitor selection connect an input capacitor which is ov er 10 uf between each vin pin and power ground. it should be placed close to the device as possible. vreg capacitor connect 1uf ceramic capacitor to vreg pin. bootstrap capacitor connect 0.1uf ceramic capacitor be tween lx pin and boost pin. feedback capacitor when using auto pfm mode, it is recommended to connect feedback capacitor in parallel to high side output voltage setting resistor to improve phase characteristic at auto pfm mode. components example vin (v) vout (v) l (uh) cout (uf) c fb (pf) auto pfm mode pwm mode 12 5v 3.3 22 to 44 47 - 3.3v 3.3 22 to 44 47 - 1.2v 3.3 22 to 44 t. b. d . - v out r1 r2 fb feedback capacitor vout
page 24 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 notes on use vin applied voltage be sure to apply the same voltage tovin1 pin and vin2 pin. pattern wiring to actually perform pattern wiring, separate a ground of control signal from a ground of a power line, so that these grounds do not have a common impedance as much as possible. connection of exposed pad htssop package has an exposed pad on the bottom to improve radiation performance. on the mounting board, connect this exposed pad to pgnd or gnd. fixed usage of control input pin when en pin and x_autopfm pin are fixed, connect to a pin listed below. input pin connect pin fixed to low level fixed to high level en1 gnd vin en2 gnd vin x_autopfm gnd vin
page 25 of 25 raa23022x raa23023x [under development] preliminar y r18ds0017ej0000 rev.0.00 aug.19.2014 package dimensions 20pin htssop renesas code : ptsp0020jf-a
all trademarks and registered trademarks are the property of their respective owners. c - 1 rev. date description page summary 0.00 aug.19. 2014 - first edition issued revision history raa23022x, raa 23023x preliminary datasheet
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